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Loop interchange : ウィキペディア英語版
Loop interchange
In compiler theory, loop interchange is the process of exchanging the order of two iteration variables used by a nested loop. The variable used in the inner loop switches to the outer loop, and vice versa. It is often done to ensure that the elements of a multi-dimensional array are accessed in the order in which they are present in memory, improving locality of reference.
For example, in the code fragment:
for i from 0 to 10
for j from 0 to 20
a() = i + j
loop interchange would result in:
for j from 0 to 20
for i from 0 to 10
a() = i + j
On occasion, such a transformation may create opportunities to further optimize, such as automatic vectorization of the array assignments.
==The utility of loop interchange==
The major purpose of loop interchange is to take advantage of the CPU cache when accessing array elements. When a processor accesses an array element for the first time, it will retrieve an entire block of data from memory to cache. That block is likely to have many more consecutive elements after the first one, so on the next array element access, it will be brought directly from cache (which is faster than getting it from slow main memory). Cache misses occur if the contiguously accessed array elements within the loop come from a different cache block, and loop interchange can help prevent this. The effectiveness of loop interchange depends on and must be considered in light of the cache model used by the underlying hardware and the array model used by the compiler.
In C programming language, array elements in the same row are stored consecutively in memory (a(), a(), a()) ‒ in row-major order. On the other hand, FORTRAN programs store array elements from the same column together (a(), a(), a()), using column-major. Thus the order of two iteration variables in the first example is suitable for a C program while the second example is better for FORTRAN. Optimizing compilers can detect the improper ordering by programmers and interchange the order to achieve better cache performance.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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